LTC4268IDKD-1#PBF【PDF 36/46 页】IC PD HIGH POWER W/CNTRL 32-DFN

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LTC4268-1

42681fc

applicaTions inForMaTion

The LTC4268-1 has an internal clamp on V

of approxi-

mately 20V. This provides some protection for the part

in the event that the switcher is off (UVLO low) and the

node is pulled high. If R

is sized correctly the part

should never attain this clamp voltage.

Control Loop Compensation

Loop frequency compensation is performed by connect-

ing a capacitor network from the output of the feedback

amplifier (V

CMP

pin) to ground as shown in Figure 17.

Because of the sampling behavior of the feedback amplifier,

compensation is different from traditional current mode

controllers. Normally only C

VCMP

is required. R

VCMP

can

be used to add a zero but the phase margin improve-

ment traditionally offered by this extra resistor is usually

already accomplished by the nonzero secondary circuit

impedance. C

VCMP2

can be used to add an additional high

frequency pole and is usually sized at 0.1 times C

VCMP

In further contrast to traditional current mode switchers,

CMP

pin ripple is generally not an issue with the LTC4268-1.

The dynamic nature of the clamped feedback amplifier

forms an effective track/hold type response, whereby the

CMP

voltage changes during the flyback pulse, but is then

held during the subsequent switch on portion of the

next cycle. This action naturally holds the V

CMP

voltage

stable during the current comparator sense action (current

mode switching).

Application Note 19 provides a method for empirically

tweaking frequency compensation. Basically it involves

introducing a load current step and monitoring the

response.

Slope Compensation

The LTC4268-1 incorporates current slope compensation.

Slope compensation is required to ensure current loop

stability when the DC is greater than 50%. In some switching

regulators, slope compensation reduces the maximum peak

current at higher duty cycles. The LTC4268-1 eliminates

this problem by having circuitry that compensates for

the slope compensation so that maximum current sense

voltage is constant across all duty cycles.

Minimum Load Considerations

At light loads, the LTC4268-1 derived regulator goes into

forced continuous conduction mode. The primary side

switch always turns on for a short time as set by the

ON(MIN)

resistor. If this produces more power than the

load requires, power will flow back into the primary during

the off period when the synchronization switch is on.

This does not produce any inherently adverse problems,

although light load efficiency is reduced.

Maximum Load Considerations

The current mode control uses the V

CMP

node voltage and

amplified sense resistor voltage as inputs to the current

comparator. When the amplified sense voltage exceeds the

CMP

node voltage, the primary side switch is turned off.

In normal use, the peak switch current increases while

FB is below the internal reference. This continues until

CMP

reaches its 2.56V clamp. At clamp, the primary side

MOSFET will turn off at the rated 100mV V

SENSE

level. This

repeats on the next cycle. It is possible for the peak primary

switch currents as referred across R

SENSE

to exceed the

VCMP

CMP

VCMP

42681 F17

VCMP2

Figure 17. V

CMP

Compensation Network

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